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M.TECH VLSI PROJECTS LIST 2018 - 19

S.No Code PROJECT TITLE Download Titles Action
1 CTVLK101 Hybrid LUT/Multiplexer FPGA Logic Architectures
2 CTVLK102 Implementation of different types of Data Encoding techniques to reduce Energy on NOC applications
3 CTVLK103 Logic Synthesis in Reversible PLA
4 CTVLK104 Energy Efficient Code Converters using Reversible Logic Gates
5 CTVLK105 Design and Implementation of FPGA Configuration Logic Block using Asynchronous Semi- Static NCL Circuits
6 CTVLK106 Contemplation of synchronous Gray Code Counter & its variants using Reversible Logic Gates
7 CTVLK107 Digital clock design using Verilog
8 CTVLK108 Improved Carry Select Adder with Reduced Area and Low Power Consumption
9 CTVLK109 Design of 16-bit ALU.
10 CTVLK110 Design i2c protocol implementation
11 CTVLK111 Design and Implementation of Optimized Fault-Tolerant Reversible Multiplier Using K-Algorithm
12 CTVLK112 Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs
13 CTVLK113 Design of 128 bit RAM
14 CTVLK114 An FPGA Implementation of Energy Efficient Code Converters Using Reversible Logic Gates
15 CTVLK115 Design spi protocol implementation.
16 CTVLK116 A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits
17 CTVLK117 Design of electronic voting mechine.
18 CTVLK118 DESIGN OF HIGH SPEED MULTIPLIER BY USING DADDA MULTIPLIER
19 CTVLK119 Probability-Driven Multi-bit Flip-Flop Integration With Clock Gating
20 CTVLK120 Design and synthesis of combinational circuits using reversible decoder in Xilinx
21 CTVLK121 Design and analysis of multiplier using approximate 15-4 compressor
22 CTVLK122 Design counter and verifying counter by using clock block .
23 CTVLK123 Design of Multiplexer using Reversible Gates
24 CTVLK124 Design and Analysis of 4-2 Compressor for Arithmetic Application
25 CTVLK125 A New Logic Encryption Strategy Ensuring Key Interdependency
26 CTVLK126 Design of Logic gates in back-end
27 CTVLK127 Design 32x32 vedik multipleare.
28 CTVLK128 Design of FIFO using HDL
29 CTVLK129 FPGA Implementation of an Advanced Traffic Light Controller using Verilog HDL
30 CTVLK130 Implementation of Universal Asynchronous Receiver and Transmitter
31 CTVLK131 Low-Power Programmable PRPG With Test Compression Capabilities
32 CTVLK132 Double fault tolerant full adder design using fault localization
33 CTVLK133 In Field test for Permanent faults in FIFO buffers of NOC routers
34 CTVLK134 Design 4x4 vedik multiplear
35 CTVLK135 Implementation of Testable Reversible Sequential Circuit on FPGA
36 CTVLK136 Development of Efficient VLSI Architecture for Speech Processing in Mobile Communication
37 CTVLK137 Design of Power and Area Efficient Approximate Multipliers

M.TECH VLSI PROJECTS LIST 2017 - 18

S.No Code PROJECT TITLE Download Titles Action
1 CTVL701 A Slack-based Approach to Efficiently Deploy Radix 8 Booth Multipliers
2 CTVL702 Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
3 CTVL703 Design of Power and Area Efficient Approximate Multipliers
4 CTVL704 Design And Synthesis Of Combinational Circuits Using Reversible Decoder In Xilinx
5 CTVL705 Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity
6 CTVL706 Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities
7 CTVL707 Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters
8 CTVL708 Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields
9 CTVL709 Time-Encoded Values for Highly Efficient Stochastic Circuits
10 CTVL710 A new high performance VLSI architecture for LMS adaptive filter using Distributed Arithmetic
11 CTVL711 Optimal VLSI delay Tuning by Space Tapering with clock-Tree Application
12 CTVL712 Development of efficient VLSI architecture for Speech-Processing in Mobile communication
13 CTVL713 High speed and low power VLSI architecture for inexact Speculative adder
14 CTVL714 Low cost roll back to improve fault-tolerance in VLSI circuits
15 CTVL715 Low latency VLSI architecture for neural cross frequency coupling analysis
16 CTVL716 An Enhancement of cross talk-Avoidance code based on Fibonacci Numerical system for through silicon vias
17 CTVL717 Interspike-interval-Based Analog spike-time dependent encoder for Neuromorphic Processor
18 CTVL718 Testing multiple stuck at faults of ROBDD based combinational circuit design
19 CTVL719 Self-controlled high performance pre-charge free Content Addressable Memory
20 CTVL720 Approximate error detection with stochastic checkers
21 CTVL721 Weighted Partitioning for Fast Multiplier less Multiple-Constant Convolution Circuit
22 CTVL722 On the Implementation of Computation-in-Memory Parallel Adder
23 CTVL723 Design and verification of improved hamming code (ECC) using Verilog
24 CTVL724 Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication
25 CTVL725 Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map
26 CTVL726 Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
27 CTVL727 An Efficient Fault-Tolerance Design for Integer Parallel Matrix–Vector Multiplications
28 CTVL728 Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level
29 CTVL729 Architecture Design of a Memory Subsystem for Massive MIMO Baseband Processing
30 CTVL730 Design of an Area-Efficient Million-Bit Integer Multiplier Using Double Modulus NTT
31 CTVL731 Resource efficient SRAM based ternary content Addressable Memory
32 CTVL732 High-Speed Parallel LFSR architectures based on improved state-space Transformations
33 CTVL733 VLSI design of 64 bit*64 bit high performance multiplier with Redundant Binary encoding
34 CTVL734 Sign-magnitude encoding for efficient VLSI Realization of Decimal Multiplication
35 CTVL735 Soft error Rate Reduction of combinational circuits using gate sizing in the presence of process variations
36 CTVL736 Adaptive multi-bit cross talk –Aware error control coding scheme for On chip-communication
37 CTVL737 A Fault Tolerance Technique for combinational circuits based on selective Transistor Redundancy
38 CTVL738 Dependency Structure matrix modeling for Digital Design using Verilog HDL
39 CTVL739 Design and analysis of multimode Single Precision Floating Point ALU using Verilog
40 CTVL740 Verilog implementation of Digital Modulation Techniques BPSK and QPSK using HDL Verilog
41 CTVL741 Simulation of 23*23 bit Multiplication algorithm in Vedic mathematics using Verilog
42 CTVL742 A Novel algorithm and architecture for a high-through put VLSI implementation of DST using Short Pseudo-cycle convolutions
43 CTVL743 Majority-Logic-Optimized Parallel prefix carry look ahead adder Families using Adiabatic Quantum-Flux-Parametron Logic
44 CTVL744 DFT computation using gauss-Eisenstein Basis : FFT algorithms and VLSI architecture
45 CTVL745 Design of MAC unit in artificial neural network architecture using Verilog HDL
46 CTVL746 Generation of PWM using Verilog
47 CTVL747 VLSI implementation of a cost-efficient micro control unit an asymmetric encryption for Wireless Body sensor Networks
48 CTVL748 A New logic encryption Strategy ensuring Key Interpedency
49 CTVL749 Probability-Driven Multi bit Flip-Flop Integration With Clock Gating
50 CTVL750 A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

M.TECH VLSI PROJECTS LIST 2016 - 17

S.No Code PROJECT TITLE Download Titles Action
1 CTVL101 A low-power broad-bandwidth noise cancellation VLSI circuit design for in-ear headphones
2 CTVL102 Streaming elements for FPGA signal and image processing accelerators
3 CTVL103 A low-voltage radiation-hardened 13T SRAM bit cell for ultralow power space applications
4 CTVL104 High-speed and energy-efficient carry skip adder operating under a wide range of supply voltage levels
5 CTVL105 Low-cost high-performance VLSI architecture for Montgomery modular multiplication
6 CTVL106 A thermal energy harvesting power supply with an internal startup circuit for pacemakers
7 CTVL107 A high-speed FPGA implementation of an RSD-based ECC processor
8 CTVL108 Knowledge-based neural network model for FPGA logical architecture development
9 CTVL109 A practical logic obfuscation technique for hardware security
10 CTVL110 Floating-point butterfly architecture based on binary signed-digit representation
11 CTVL111 A mixed-decimation MDF architecture for radix- 2 power k parallel FFT
12 CTVL112 A generalized algorithm and reconfigurable architecture for efficient and scalable orthogonal approximation of DCT
13 CTVL113 Mixing drivers in clock-tree for power supply noise reduction
14 CTVL114 An Efficient Code Compression Technique for Embedded Systems
15 CTVL115 Implementation of dynamic rams with clock gating circuits using Verilog HDL
16 CTVL116 Implementation and analysis of different line coding schemes using Verilog.
17 CTVL117 Low-power split-radix FFT processors using radix-2 butterfly units
18 CTVL118 Reducing power, leakage, and area of standard-cell ASICS using threshold logic flip-flops
19 CTVL119 A fast process-variation-aware mask optimization algorithm with a novel intensity modeling.
20 CTVL120 A capacitor-less LDO with high-frequency PSR suitable for a wide range of on-chip capacitive loads
21 CTVL121 Energy and area efficient three-input XOR/XNORS with systematic cell design methodology
22 CTVL122 A high-performance fir filter architecture for fixed and reconfigurable applications
23 CTVL123 Application mapping onto mesh-based network-on-chip using discrete particle swarm optimization
24 CTVL124 An ultralow power multi rate FSK demodulator for high-speed biomedical zero if receivers
25 CTVL125 One minimum only trellis decoder for non-binary low-density parity check codes
26 CTVL126 The VLSI architecture of a highly efficient de-blocking filter for HEVC systems
27 CTVL127 Algorithm and architecture of configurable joint detection and decoding for MIMO wireless communications
with convolution codes.
28 CTVL128 VLSI implementation of text to image encryption algorithm based on private key encryption.
29 CTVL129 Statistical framework and built-in self speed-binning system for speed binning using on-chip ring oscillators.
30 CTVL130 Source coding and pre-emphasis for double-edged pulse width modulation serial communication.
31 CTVL131 A configurable parallel hardware architecture for efficient integral histogram image computing.
32 CTVL132 A new CDMA encoding/decoding method for on-chip communication network.
33 CTVL133 Floating-point butterfly architecture based on binary signed-digit representation.
34 CTVL134 Optimized built-in self-repair for multiple memories.
35 CTVL135 Online testing for three fault models in reversible circuits.
36 CTVL136 A novel realization of reversible LFSR for its application in cryptography.
37 CTVL137 Design of priority encoding based reversible comparators.
38 CTVL138 Low-power and area-efficient shift register using pulsed latches.
39 CTVL139 Design of a power optimal reversible fir filter for speech signal processing.
40 CTVL140 New regular radix-8 scheme for elliptic curve scalar multiplication without pre-computation.
41 CTVL141 Exact and approximate algorithms for the filter design optimization problem.
42 CTVL142 In-field test for permanent faults in FIFO buffers of NoC routers
43 CTVL143 Fast code design for overloaded code-division multiplexing systems.
44 CTVL144 A complexity scaling method for the lanczos kernel in fixed-point arithmetic.
45 CTVL145 Piecewise-functional broadside tests based on reachable states.
46 CTVL146 Area speed efficient modular architecture for GF multiplier dedicated for cryptographic applications.
47 CTVL147 Modulation classification of single input multiple output signals using asynchronous sensors
48 CTVL148 Modified Wallace tree multiplier using efficient square root carry select adder
49 CTVL149 Input-based dynamic reconfiguration of approximate arithmetic units for video encoding
50 CTVL150 Low-cost high-performance VLSI architecture for Montgomery modular multiplication
51 CTVL151 Advanced low power RISC processor design using MIPS instruction set
52 CTVL152 VLSI –assisted non rigid registration using modified demons algorithm
53 CTVL153 Timing error tolerance in small core designs for soc applications
54 CTVL154 Synthesis of genetic cloth with combinational biologic circuits
55 CTVL155 A multi cycle test set based on a two cycle test set with constant primary input vectors
56 CTVL156 A low power and high-sensing margin non-volatile full adder using racetrack memory.
57 CTVL157 High performances fir filters architecture for fixed and reconfigurable applications fir filter.
58 CTVL158 On the analysis of reversible booth’s multiplier
59 CTVL159 Optimized logarithmic barrel shifter in reversible logic synthesis
60 CTVL160 Dynamically reconfigurable multi-ASIP architecture for multi standard and multimode turbo decoding.
61 CTVL161 Reliable power gating with NBTI aging benefits
62 CTVL162 Accuracy improvement of energy prediction for solar-energy-powered embedded systems
63 CTVL163 Defect- and variation-tolerant logic mapping in nano-crossbar using bipartite matching and memetic algorithm
64 CTVL164 A New Efficient RNS Reverse Converter for the 4-Moduli Set {2^n,2^n+1, 2^n-1, 2^(2n+1)-1}
65 CTVL165 VLSI implementation of an adaptive edge enhanced color interpolation processor for real-time video applications
66 CTVL166 VLSI implementation of an adaptive edge enhanced color interpolation processor for real-time video applications
67 CTVL167 Enhanced memory reliability against multiple cell upsets using decimal matrix code
68 CTVL168 Low-power programmable PRPG with test compression capabilities.
69 CTVL169 RTL design and VLSI implementation of an efficient convolution encoder and adaptive viterbi decoder.
70 CTVL170 A novel fault detection and correction technique for memory applications.
71 CTVL171 Recursive approach to the design of a parallel self timed adder.
72 CTVL172 A variation-aware preferential design approach for memory-based reconfigurable computing.
73 CTVL173 Design of self-timed reconfigurable controllers for parallel synchronization via wagging.
74 CTVL174 A generalization of addition chains and fast inversions in binary fields
75 CTVL175 Communication optimization of iterative sparse matrix – vector multiply on GPUS and FPGA
76 CTVL176 Low energy two stage algorithm for high efficiency epileptic seizure detection
77 CTVL177 Novel reconfigurable hardware architecture for polynomial matrix multiplications
78 CTVL178 Asynchronous domino logic pipeline design based on constructed critical data path
79 CTVL179 A generalization of addition chains and fast inversions in binary codes
80 CTVL180 A synergetic use of bloom filters for error detection and correction
81 CTVL181 Single-ended Schmitt-trigger-based robust low-power SRAM cell
82 CTVL182 Improving nested loop pipelining on coarse-grained reconfigurable architectures
83 CTVL183 Modeling and optimization of memristor and STT-RAM-based memory for low-power applications
84 CTVL184 Area-delay-power efficient fixed-point LMS adaptive filter with low adaption delay.
85 CTVL185 Analysis and design of a low-voltage low-power double-tail comparator.
86 CTVL186 Enhanced memory reliability against multiple cell upsets using decimal matrix code
87 CTVL187 Design and analysis of approximate compressors for multiplication
88 CTVL188 Ultra-high throughput low power packet classification
89 CTVL189 VLSI implementation of a high speed single precision floating point unit using Verilog
90 CTVL190 Novel high speed Vedic mathematics multiplier using compressor.
91 CTVL191 A high speed binary floating point multiplier using dadda algorithm.
92 CTVL192 Enhanced built-in self-repair techniques for improving fabrication yield and reliability of embedded memories
93 CTVL193 Mixing drivers in clock-tree for power supply noise reduction
94 CTVL194 Signal design for multiple antenna systems with spatial multiplexing and non coherent reception
95 CTVL195 A leakage compensation design for low supply voltage SRAM
96 CTVL196 Pre-charge-free, low-power content-addressable memory
97 CTVL197 Designing of VGA Character String Display Module Base on FPGA
98 CTVL198 Two-step optimization approach for the design of multiplier less linear-phase fir filters.
99 CTVL199 High-speed, low-power, and highly reliable frequency multiplier for DLL-based clock generator
100 CTVL200 Total jitter of delay-locked loops due to four main jitter sources

M.TECH VLSI PROJECTS LIST 2015 - 16

S.No Code PROJECT TITLE Download Titles Action
1 CTVL501 NEW REGULAR RADIX-8 SCHEME FOR ELLIPTIC CURVE SCALAR MULTIPLICATION WITHOUT PRE-COMPUTATION
2 CTVL502 LOW-POWER PROGRAMMABLE PRPG WITH TEST COMPRESSION CAPABILITIES
3 CTVL503 DESIGN AND DEVELOPMENT OF EFFICIENT REVERSIBLE FLOATING POINT ARITHMETIC UNIT
4 CTVL504 A SELF-POWERED HIGH-EFFICIENCY RECTIFIER WITH AUTOMATIC RESETTING OF TRANSDUCER
CAPACITANCE IN PIEZOELECTRIC ENERGY HARVESTING SYSTEMS
5 CTVL505 REDUCING RMS NOISE IN CMOS DYNAMIC RECONFIGURABLE LATCHED COMPARATOR IN 50 NM
6 CTVL506 COMMUNICATION OPTIMIZATION OF ITERATIVE SPARSE MATRIX - VECTOR MULTIPLY ON GPUS AND FPGAS
7 CTVL507 DESIGN OF A COMPACT REVERSIBLE CARRY LOOK-AHEAD ADDER USING DYNAMIC PROGRAMMING
8 CTVL508 FULLY REUSED VLSI ARCHITECTURE OF FM0/MANCHESTER ENCODING USING SOLS TECHNIQUE FOR
DSRC APPLICATIONS
9 CTVL509 DESIGN OF FULL ADDER CIRCUIT USING DOUBLE GATE MOSFET
10 CTVL510 DESIGN OF ADIABATIC DYNAMIC DIFFERENTIAL LOGIC FOR DPA-RESISTANT SECURE INTEGRATED CIRCUITS
11 CTVL511 VLSI COMPUTATIONAL ARCHITECTURES FOR THE ARITHMETIC COSINE TRANSFORM
12 CTVL512 DESIGN OF OPTIMIZED REVERSIBLE BINARY AND BCD ADDERS
13 CTVL513 EFFICIENT CODING SCHEMES FOR FAULT-TOLERANT PARALLEL FILTERS
14 CTVL514 IMPLEMENTATION OF TESTABLE REVERSIBLE SEQUENTIAL CIRCUIT ON FPGA
15 CTVL515 A CLOSED-LOOP RECONFIGURABLE SWITCHED-CAPACITOR DC-DC CONVERTER FOR SUB-MW ENERGY
HARVESTING APPLICATIONS
16 CTVL516 LOW-POWER AND AREA-EFFICIENT SHIFT REGISTER USING PULSED LATCHES
17 CTVL517 SCAN TEST BANDWIDTH MANAGEMENT FOR ULTRALARGE - SCALE SYSTEM-ON-CHIP ARCHITECTURES
18 CTVL518 PARITY PRESERVING ADDER/SUBTRACT OR USING A NOVEL REVERSIBLE GATE
19 CTVL519 A MULTICYCLE TEST SET BASED ON A TWO-CYCLE TEST SET WITH CONSTANT PRIMARY INPUT VECTORS
20 CTVL520 DESIGN OF A POWER OPTIMAL REVERSIBLE FIR FILTER FOR SPEECH SIGNAL PROCESSING
21 CTVL521 ALGORITHM AND ARCHITECTURE FOR A LOW-POWER CONTENT-ADDRESSABLE MEMORY BASED ON
SPARSE CLUSTERED NETWORKS
22 CTVL522 ONLINE TESTING FOR THREE FAULT MODELS IN REVERSIBLE CIRCUITS
23 CTVL523 A LOW-POWER HYBRID RO PUF WITH IMPROVED THERMAL STABILITY FOR LIGHTWEIGHT APPLICATIONS
24 CTVL524 A NOVEL REALIZATION OF REVERSIBLE LFSR FOR ITS APPLICATION IN CRYPTOGRAPHY
25 CTVL525 VARIABLE LATENCY SPECULATIVE HAN-CARLSON ADDER
26 CTVL526 DESIGN OF PRIORITY ENCODING BASED REVERSIBLE COMPARATORS
27 CTVL527 RECURSIVE APPROACH TO THE DESIGN OF A PARALLEL SELF-TIMED ADDER
28 CTVL528 A GENERALIZED ALGORITHM AND RECONFIGURABLE ARCHITECTURE FOR EFFICIENT AND SCALABLE
ORTHOGONAL APPROXIMATION OF DCT
29 CTVL529 HIGH-THROUGHPUT LOW-ENERGY SELF-TIMED CAM BASED ON REORDERED OVERLAPPED SEARCH MECHANISM
30 CTVL530 IMPLEMENTATION OF FLOATING POINT MAC USING RESIDUE NUMBER SYSTEM
31 CTVL531 ARCHITECTURES AND ALGORITHAM FOR IMAGE AND VIDEO PROCESSING USING FPGA – BASED PLAT FORM
32 CTVL532 HARDWARE EFFICIENT MIXED RADIX-25/16/9 FFT FOR LTE SYSTEMS
33 CTVL533 PERFORMANCE AND EVALUATION OF LOOPBACK VIRTUAL CHANNEL ROUTER WITH HETEROGENEOUS
ROUTER FOR ON CHIP NETWORK
34 CTVL534 ANALYSIS AND DESIGN OF A LOW-VOLTAGE LOW-POWER DOUBLE-TAIL COMPARATOR
35 CTVL535 EFFICENT RELIZATION OF DA BASED FIR FILTER USING VERILOG
36 CTVL536 A LOW-COST, SYSTEMATIC METHODOLOGY FOR SOFT ERROR ROBUSTNESS OF LOGIC CIRCUITS
37 CTVL537 ON-CHIP CODE WORD GENERATION TO COPE WITH CROSSTALK
38 CTVL538 LOW COMPLEXITY-HIGH THROUGHPUT QC-LDPC ENCODER
39 CTVL539 A NOVEL VLSI DHT ALGORITHAM FOR HIGHLY AND ACITECTURE MODELAR PARALEL
40 CTVL540 EXPLOITING SAME TAG BITS TO IMPROVE THE RELIABILITY OF THE CACHE MEMORIES
41 CTVL541 EFFICENT HARD WARE ARCHITUCTURE OF NT PAIRING ACELERATOR OVER CHARASTRICTIC TREE
42 CTVL542 CONSTRUCTIONS OF MEMORYLESS CROSSTALK AVOIDANCE CODES VIA C-TRANSFORM
43 CTVL543 AREA–DELAY–POWER EFFICIENT CARRY-SELECT ADDER
44 CTVL544 LOW-POWER PULSE-TRIGGERED FLIP-FLOP DESIGN BASED ON A SIGNAL FEED-THROUGH SCHEME
45 CTVL545 VLSI DESIGN OF LARGE NUMBER MULTIPLIER FOR FULLY HOMOMORPHIC ENCRYPTION
46 CTVL546 TEST PATTERNS OF MULTIPLE SIC VECTORS: THEORY AND APPLICATION IN BIST SCHEMES
47 CTVL547 ENERGY EFFICIENCY OPTIMIZATION THROUGH CODESIGN OF THE TRANSMITTER AND RECEIVER IN
HIGH-SPEED ON-CHIP INTERCONNECTS
48 CTVL548 A REAL-TIME MOTION-FEATURE-EXTRACTION VLSI EMPLOYING DIGITAL-PIXEL-SENSOR-BASED
PARALLEL ARCHITECTURE
49 CTVL549 SELF-TIMED LOGIC AND THE DESIGN OF SELF-TIMED ADDERS
50 CTVL550 DESIGN AND DEVELOPMENT OF AUTOMATIC VISUAL INSPECTION SYSTEM FOR PCB MANUFACTURING
51 CTVL551 AREA-DELAY-POWER EFFICIENT FIXED-POINT LMS ADAPTIVE FILTER WITH LOW ADAPTATION-DELAY
52 CTVL552 FULLY REUSED VLSI ARCHITECTURE OF FM0/MANCHESTER ENCODING USING SOLS TECHNIQUE FOR
DSRC APPLICATIONS
53 CTVL553 FPGA DESING OF RECONFIGURABLE PROCESOR USING VLSI
54 CTVL554 AREA–DELAY–POWER EFFICIENT CARRY-SELECT ADDER
55 CTVL555 FAULT TOLERANT PARALLEL FILTERS BASED ON ERROR CORRECTION CODES
56 CTVL556 A HIGH PERFORMANCE DDR3 SDRAM CONTROLLER
57 CTVL557 VLSI IMPLEMENTATION OF IMAGE SCALING PROCESSOR
58 CTVL558 PORTABLE CAMERA BASED ASSISTINCE LABLE READING FOR BLIND PERSON
59 CTVL559 SOFTWARE/HARDWARE PARALLEL LONG-PERIOD RANDOM NUMBER GENERATION FRAMEWORK BASED ON
THE WELL METHOD
60 CTVL560 LOW-COMPLEXITY MULTIPLIER LESS CONSTANT ROTATORS BASED ON COMBINED COEFFICIENT SELECTION
AND SHIFT-AND-ADD IMPLEMENTATION (CCSSI)
61 CTVL561 A NOVEL APPROACH TO REALIZE BUILT-IN-SELF-TEST(BIST) ENABLED UART USING VHDL
62 CTVL562 AN OPTIMIZED MODIFIED BOOTH RECORDER FOR EFFICIENT DESIGN OF THE ADD-MULTIPLY OPERATOR
63 CTVL563 LOW-POWER PULSE-TRIGGERED FLIP-FLOP DESIGN BASED ON A SIGNAL FEED-THROUGH SCHEME
64 CTVL564 LOW-COMPLEXITY LOW-LATENCY ARCHITECTURE FOR MATCHING OF DATA ENCODED WITH HARD
SYSTEMATIC ERROR-CORRECTING CODES
65 CTVL565 DESIGN OF EFFICIENT BINARY COMPARATOR IN QUANTUM DOT CELLAR AUTOMATA
66 CTVL566 DATA ENCODING TECHNIQUES FOR REDUCING ENERGY CONSUMPTION IN NETWORK ON CHIP
67 CTVL567 SCALABLE DIGITAL COMOS COMPARATOR USING A PARALLEL PREFIX TREE

M.TECH VLSI PROJECTS LIST 2014 - 15

S.No Code PROJECT TITLE Download Titles Action
1 CTVL101 Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems
2 CTVL102 Fault Tolerant Parallel Filters Based on Error Correction Codes
3 CTVL103 Efficient Hardware Architecture of η T Pairing Accelerator Over Characteristic Three
4 CTVL104 Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging
5 CTVL105 Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories
6 CTVL106 Energy-Efficient Soft-Input Soft-Output Signal Detector for Iterative MIMO Receivers
7 CTVL107 Effects of Intermittent Faults on the Reliability of a Reduced Instruction Set Computing (RISC) Microprocessor
8 CTVL108 A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise D f T Scheme
9 CTVL109 A Low Complexity-High Throughput QC-LDPC Encoder
10 CTVL110 Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line
11 CTVL111 Energy Efficiency Optimization Through Code sign of the Transmitter and Receiver in High-Speed On-Chip Interconnects
12 CTVL112 A Real-Time Motion-Feature-Extraction VLSI Employing Digital-Pixel-Sensor-Based Parallel Architecture
13 CTVL113 Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
14 CTVL114 Self-Timed Logic and the Design of Self-Timed Adders
15 CTVL115 Compact Test Generation With an Influence Input Measure for Launch-On-Capture Transition Fault Testing
16 CTVL116 High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism
17 CTVL117 Constructions of Memory less Crosstalk Avoidance Codes via C-Transform
18 CTVL118 Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications
19 CTVL119 VLSI Design of a Large-Number Multiplier for Fully Holomorphic Encryption
20 CT1VL120 Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme
21 CTVL121 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay
22 CTVL122 An Optimized Modified Booth Recorder for Efficient Design of the Add-Multiply Operator
23 CTVL123 Area-Delay Efficient Binary Adders in QCA
24 CTVL124 On-Chip Code word Generation to Cope With Crosstalk
25 CTVL125 Low-Complexity Multiplier less Constant Rotators Based on Combined Coefficient Selection and Shift-and-Add
Implementation (CCSSI)
26 CTVL126 Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method
27 CTVL127 Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding
28 CTVL128 Crosstalk-Aware Multiple Error Detection Scheme Based on Two-Dimensional Parities for Energy Efficient Network on Chip
29 CTVL129 Efficient Integer DCT Architectures for HEVC
30 CT1VL130 Comments on “Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding”
31 CTVL131 Recursive Approach to the Design of a Parallel Self-Timed Adder Design and Estimation of delay, power and area for
Parallel prefix adders
32 CTVL132 On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions
33 CTVL133 A Novel Parallel Multiplier for 2’s Complement Numbers Using Booth’s Recoding Algorithm
34 CTVL134 High Speed Convolution and DE convolution Algorithm (Based on Ancient Indian Vedic Mathematics)
35 CTVL135 FPGA Based Partial Reconfigurable FIR filter design
36 CTVL136 Design and Estimation of delay, power and area for Parallel prefix adders
37 CTVL137 Multiplication Acceleration Through Quarter Precision Wallace Tree Multiplied
38 CTVL138 New Implementations of the WG Stream Cipher
39 CTVL139 Fast Radix-10 Multiplication Using Redundant BCD Codes
40 CT1VL140 Area–Delay–Power Efficient Carry-Select Adder
41 CTVL141 Double-Fault Tolerant Architecture Design for Digital Adder
42 CTVL142 Implementation Of Floating Point Mac Using Residue Number System
43 CTVL143 Compact Implementation of SHA3-512 on FPGA
44 CTVL144 A novel approach to realize Built-in-self-test(BIST) enabled UART using VHDL
45 CTVL145 High Throughput Architecture for the Advanced Encryption Standard Algorithm

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