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B.TECH VLSI MAJOR PROJECTS LIST 2018 - 19

S.No Code PROJECT TITLE Download Titles Action
1 CTVLK101 Hybrid LUT/Multiplexer FPGA Logic Architectures
2 CTVLK102 Implementation of different types of Data Encoding techniques to reduce Energy on NOC applications
3 CTVLK103 Logic Synthesis in Reversible PLA
4 CTVLK104 Energy Efficient Code Converters using Reversible Logic Gates
5 CTVLK105 Design and Implementation of FPGA Configuration Logic Block using Asynchronous Semi- Static NCL Circuits
6 CTVLK106 Contemplation of synchronous Gray Code Counter & its variants using Reversible Logic Gates
7 CTVLK107 Digital clock design using Verilog
8 CTVLK108 Improved Carry Select Adder with Reduced Area and Low Power Consumption
9 CTVLK109 Design of 16-bit ALU.
10 CTVLK110 Design i2c protocol implementation
11 CTVLK111 Design and Implementation of Optimized Fault-Tolerant Reversible Multiplier Using K-Algorithm
12 CTVLK112 Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs
13 CTVLK113 Design of 128 bit RAM
14 CTVLK114 An FPGA Implementation of Energy Efficient Code Converters Using Reversible Logic Gates
15 CTVLK115 Design spi protocol implementation.
16 CTVLK116 A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits
17 CTVLK117 Design of electronic voting mechine.
18 CTVLK118 DESIGN OF HIGH SPEED MULTIPLIER BY USING DADDA MULTIPLIER
19 CTVLK119 Probability-Driven Multi-bit Flip-Flop Integration With Clock Gating
20 CTVLK120 Design and synthesis of combinational circuits using reversible decoder in Xilinx
21 CTVLK121 Design and analysis of multiplier using approximate 15-4 compressor
22 CTVLK122 Design counter and verifying counter by using clock block .
23 CTVLK123 Design of Multiplexer using Reversible Gates
24 CTVLK124 Design and Analysis of 4-2 Compressor for Arithmetic Application
25 CTVLK125 A New Logic Encryption Strategy Ensuring Key Interdependency
26 CTVLK126 Design of Logic gates in back-end
27 CTVLK127 Design 32x32 vedik multipleare.
28 CTVLK128 Design of FIFO using HDL
29 CTVLK129 FPGA Implementation of an Advanced Traffic Light Controller using Verilog HDL
30 CTVLK130 Implementation of Universal Asynchronous Receiver and Transmitter
31 CTVLK131 Low-Power Programmable PRPG With Test Compression Capabilities
32 CTVLK132 Double fault tolerant full adder design using fault localization
33 CTVLK133 In Field test for Permanent faults in FIFO buffers of NOC routers
34 CTVLK134 Design 4x4 vedik multiplear
35 CTVLK135 Implementation of Testable Reversible Sequential Circuit on FPGA
36 CTVLK136 Development of Efficient VLSI Architecture for Speech Processing in Mobile Communication
37 CTVLK137 Design of Power and Area Efficient Approximate Multipliers

B.TECH VLSI MAJOR PROJECTS LIST 2017 - 18

S.No Code PROJECT TITLE Download Titles Action
1 CTJV101 A System to Filter Unwanted Messages from OSN User Walls
2 CTJV102 Fully Anonymous Profile Matching in Mobile Social Networks
3 CTJV103 Mining Contracts for Business Events and Temporal Constraints in Service Engagements
4 CTJV104 Price Differentiation for Communication Networks
5 CTJV105 Sensitive Label Privacy Protection on Social Network Data
6 CTJV106 Supporting Privacy Protection in Personalized Web Search
7 CTJV107 Spatial Approximate String Search
8 CTJV108 Understanding the Performance and Potential of Cloud Computing for Scientific Applications
9 CTJV109 Fast Nearest Neighbor Search with Keywords
10 CTJV110 Towards Online Shortest Path Computation
11 CTJV11 A Load Balancing Model Based on Cloud Partitioning
12 CTJV112 Captcha as Graphical Passwords-A New Security Primitive Based on Hard AI Problems
13 CTJV13 Friendbook:A Semantic-based Friend Recommendation System for Social Networks
14 CTJV114 Stock Market Prediction Analysis
15 CTJV115 Advance Security In Cloud Computing For Military Weapons
16 CTJV116 Sub-graph Matching with Set Similarity in a Large Graph Database
17 CTJV117 Automatic Personality Classification
18 CTJV118 Active City Administration
19 CTJV119 Mail received Authentication System
20 CTJV120 Online Rental Web Portal
21 CTJV121 A novel Anti-Fishing Framework based on visual Cryptography
22 CTJV122 E-Assessment Instructor
23 CTJV123 Automatic DB Schema Generation
24 CTJV124 Client Server Protocol Implementation
25 CTJV125 Data Transmission Using Multi-Tasking-Sockets
26 CTJV126 Dual-Stenography for hiding text in video by linked list method
27 CTJV127 Hostel Management System
28 CTJV128 An Object-Oriented Web Test Model for Testing Web Applications
29 CTJV129 Attendance Management System
30 CTJV130 Friends Meeting point
31 CTJV131 SQL work bench
32 CTJV132 CARGO management system
33 CTJV133 Bug tracking system
34 CTJV1354 Hospital management system
35 CTJV135 Online examination system
36 CTJV136 Citizen card system
37 CTJV137 Company vehicle management system
38 CTJV138 Corporate recruitment system
39 CTJV139 Crime records management system
40 CTJV140 Data transmission using multi tasking sockets
41 CTJV141 Online registration for Voter card
42 CTJV142 Computerization of Ration Dispensing
43 CTJV143 Security system for DNS using Cryptography
44 CTJV144 Data leakage detecting
45 CTJV145 Certificate issue system
46 CTJV146 College event calendar
47 CTJV147 Fraud detection system
48 CTJV148 Engineering books resale management system
49 CTJV149 Material feedback system
50 CTJV150 Online book review management
51 CTJV151 Placement tracking system
52 CTJV152 Online clinic
53 CTJV153 Training hub
54 CTJV154 Online Java compiler with security editor
55 CTJV155 Detecting malicious face book applications
56 CTJV156 Connecting Social media to e-commerce for Product recommendation
57 CTJV157 Towards real-time country level location classification of worldwide tweets
58 CTJV158 A system for profiling and monitoring data base access patterns by application programs for anomaly detection
59 CTJV159 Follow but no track: privacy preserved profile publishing in cyber physical social systems
60 CTJV160 Social Q&A: An Online Social Network Based Question and Answer System
61 CTJV161 Collaborative Filtering-Based Recommendation of Online Social Voting
62 CTJV162 Efficient cache supported path planning on roads
63 CTJV163 Inference attack on browsing history of twitter users using public click analytics and twitter meta data
64 CTJV164 Automatic generation of social event story board from image click through data
65 CTJV165 Pro guard: Detecting malicious accounts in social network based online promotions
66 CTJV166 Blood Donor Symbiosis
67 CTJV167 A parallel patient treatment time prediction algorithm & its applications
68 CTJV168 Maximizing p2p file access availability in mobile adhoc networks
69 CTJV169 Online venue booking
70 CTJV170 Finding verb for written for written test
71 CTJV171 Weather report management
72 CTJV172 Soci Rank: Identifying and Ranking Prevalent News Topics Using Social Media Factors
73 CTJV173 Hybrid page rank algorithms
74 CTJV174 Detecting Stress Based on Social Interactions in Social Networks
75 CTJV175 Document clustering using ANT colony algorithm
76 CTJV176 Graduate selection process
77 CTJV177 Discovery of Ranking Fraud for Mobile Apps
78 CTJV178 I-injection: Towards effective collaborative filtering using an interested items
79 CTJV179 Military equipment rental system

B.TECH VLSI MAJOR PROJECTS LIST 2016 - 17

S.No Code PROJECT TITLE Download Titles Action
1 CTJV101 Investigation in fir filters to improve power efficiency and delay reduction.
2 CTJV102 Hybrid LUT/multiplexer FPGA logic architecture.
3 CTJV103 High speed, low power and highly reliable frequency multiplier for DLL based clock generator.
4 CTJV104 High throughput list decoder architecture for polar codes.
5 CTJV105 Design of digital-serial parallel filters using HDL.
6 CTJV106 Low power Wallace tree multiplier using modified full adder
7 CTJV107 An efficient floating point multiplier design for high speed applications using karatsuba algorithm
and urdhva-tiryagbhyam algorithm.
8 CTJV108 Efficient baugh-wooley architecture for signed & unsigned fast multiplication.
9 CTJV109 Online testing for three fault models using reversible digital circuits
10 CTJV110 Design and estimation of delay, power and area for parallel prefix adders.
11 CTJV111 Recursive approach to the design of a parallel self-timed adder.
12 CTJV112 Area-delay-power efficient fixed-point LMS adaptive filter with low adaptation-delay.
13 CTJV113 Implementation of canny edge detection algorithm on FPGA and displaying image through VGA interface.
14 CTJV114 A low-cost VLSI implementation for efficient removal of impulse noise.
15 CTJV115 VLSI implementation of CRC (cyclic redundancy checker) generator.
16 CTJV116 VLSI implementations of very fast and low power carry select adder circuit.
17 CTJV117 Efficient FPGA implementation of convolution.
18 CTJV118 The design of fir filter base on improved DA algorithm and its FPGA implementation.
19 CTJV119 High speed VLSI architecture for general linear feedback shift registers (LFSR) structures.
20 CTJV120 Minimization of switching activities of partial products for designing low-power multipliers
21 CTJV121 High performance complex number multiplier using booth-Wallace algorithm.
22 CTJV122 Design and verification of 8 bit hamming encoder and decoder
23 CTJV123 Aging-aware reliable multiplier design with adaptive hold logic.
24 CTJV124 Minimum parallel binary adders with nor (NAND) gates.
25 CTJV125 Design of sequential elements for low power clocking system
26 CTJV126 Implementation of sub threshold adiabatic logic for ultralow-power application.
27 CTJV127 Fault tolerant parallel filters based on error correction codes.
28 CTJV128 Variable latency speculative hancarlson adder.
29 CTJV129 Design and analysis of approximate compressors for multiplication.
30 CTJV130 Area-delay-power efficient carry select adder.
31 CTJV131 Design of testable reversible sequential circuits.
32 CTJV132 Design a DSP operations using Vedic mathematics
33 CTJV133 VLSI implementation of fast addition using quaternary signed digit number system.
34 CTJV134 Design of a power optimal reversible fir filter for speech signal processing.
35 CTJV135 A high speed binary floating point multiplier using dadda algorithm
36 CTJV136 Design of carry look ahead adder using reversible gates.
37 CTJV137 VLSI design of a large – number multiplier for fully – homo morphic encryption.
38 CTJV138 Low power dual edge triggered flip-flop
39 CTJV139 Design of Low Power Multiplier using Compound Constant Delay Logic Style.
40 CTJV140 Designing efficient online testable reversible adders.
41 CTJV141 High performance complex number multiplier using booth-Wallace algorithm.
42 CTJV142 Low power square and cube architectures using Vedic sutras
43 CTJV13 Combinational design of s-box and inverse s-box using Verilog for high speed encryption
44 CTJV144 Area speed efficient modular architecture for GF multiplier dedicated for cryptographic applications
45 CTJV145 Design and implementation of 64 bit MAC for DSP applications
46 CTJV146 Parity preserving adder/subtractor using a novel reversible gate
47 CTJV147 VLSI design and implementation of encryption and decryption using VHDL/VERILOGHDL
48 CTJV148 VLSI design and implementation of arithmetic logic unit using VHDL/VERILOGHDL
49 CTJV149 Implementation of secure hash algorithm- 1using Verilog.
50 CTJV150 Design of advanced encryption standard using VHDL/HDL.
51 CTJV151 Energy consumption of VLSI decoder.
52 CTJV152 Realization of 4 to 16 reversible decoder using Verilog
53 CTJV153 Realization of multiplier design with novel adaptive hold logic using Verilog.
54 CTJV154 A low power 16 bit Vedic divider for high speed VLSI applications.
55 CTJV155 VLSI implementation of high speed MAC unit using karatsuba multiplication technique.
56 CTJV156 VLSI implementation of 32-bit unsigned multiplier using CSLA&CLAA.
57 CTJV157 Performance evaluation of different multipliers in VLSI using Verilog.
58 CTJV158 VLSI implementation of discrete linear convolution using Vedic mathematics (real and complex numbers)
59 CTJV159 VLSI implementation of high speed area efficient arithmetic unit using Vedic mathematics
60 CTJV160 FPGA design of reconfigurable binary processor using VLSI.
61 CTJV161 Comparative performance analysis of XOR/XNOR function based high-speed CMOS full adder circuits
62 CTJV162 Design of fast counting bloom filter using verilog
63 CTJV163 Implementation of image processing lab using Xilinx system generator
64 CTJV164 Constructions of memory less crosstalk avoidance codes via c-transform
65 CTJV165 High performance nibble multiplexer using modified adiabatic logic
66 CTJV166 Design of low power, high performance 2-4 and 4-16 mixed-logic line decoders.
67 CTJV167 Design of high speed multiplier using modified booth algorithm with hybrid carry look-ahead adder.
68 CTJV168 Design of reversible 32-bit BCD add-subtract unit using parallel pipelined method.
69 CTJV169 Design and analysis of approximate compressors for multiplication.
70 CTJV170 Low-power and area-efficient shift register using pulsed latches
71 CTJV171 Ultralow-energy variation-aware design: adder architecture study.
72 CTJV172 Low-quantum cost circuit constructions for adder and symmetric Boolean functions
73 CTJV173 A modified partial product generator for redundant binary multipliers
74 CTJV174 A 32 bit MAC unit design using Vedic multiplier and reversible logic gate.
75 CTJV175 An efficient approach to design a compact reversible programmable logic array
76 CTJV176 Approach to design a compact reversible low power binary comparator.
77 CTJV177 The design of high performance barrel integer adder.
78 CTJV178 A high speed binary floating point multiplier using dadda algorithm.
79 CTJV179 An approach to design a multiplexer based module of a novel reversible gate for FPGA architecture.
80 CTJV180 Low power array multiplier using modified full adder
81 CTJV181 Fully reused VLSI architecture of fm0/Manchester encoding using sols technique for DSRC applications
82 CTJV182 Implementation of a flexible and synthesizable FFT processor.
83 CTJV183 Low power Wallace tree multiplier using modified full adder.
84 CTJV184 Fault tolerant parallel filters based on error correction codes.
85 CTJV185 Design of a compact reversible carry look-ahead adder using dynamic programming.
86 CTJV186 Data encoding techniques for reducing energy consumption in network on chip.
87 CTJV187 Area-efficient 3-input decimal adders using simplified carry and sum vectors.
88 CTJV188 Design and analysis of inexact floating-point adders.
89 CTJV189 Modified Wallace tree multiplier using efficient square root carry select adder.
90 CTJV190 Two-step optimization approach for the design of multiplier less linear-phase fir filters.
91 CTJV191 Pre-encoded multipliers based on non-redundant radix-4 signed-digit encoding.
92 CTJV192 High-speed and energy-efficient carry skip adder operating under a wide range of supply voltage levels.
93 CTJV193 Digital multiplier less realization of two-coupled biological hind marsh–rose neuron model.
94 CTJV194 Recursive approach to the design of a parallel self-timed adder.
95 CTJV195 Efficient coding schemes for fault-tolerant parallel filters.
96 CTJV196 An improved design of a reversible fault tolerant LUT-based FPGA.
97 CTJV197 Flexible DSP accelerator architecture exploiting carry-save arithmetic.
98 CTJV198 Low power 8-bit ALU design using full adder and multiplexer.
99 CTJV199 Energy and area efficient three-input XOR/XNORS with systematic cell design methodology.
100 CTJV200 A novel realization of LFSR for cryptographic applications

B.TECH VLSI MAJOR PROJECTS LIST 2015 - 16

S.No Code PROJECT TITLE Download Titles Action
1 CTJV101 HIGH-THROUGHPUT LOW-ENERGY SELF-TIMED CAM BASED ON REORDERED
OVERLAPPED SEARCH MECHANISM
2 CTJV102 IMPLEMENTATION OF FLOATING POINT MAC USING RESIDUENUMBER SYSTEM
3 CTJV103 ARCHITECTURES AND ALGORITHAM FOR IMAGE AND VIDEO PROCESSING
USING FPGA – BASED PLAT FORM
4 CTJV104 HARDWARE EFFICIENT MIXED RADIX-25/16/9 FFT FOR LTE SYSTEMS
5 CTJV105 PERFORMANCE AND EVALUATION OF LOOPBACK VIRTUAL CHANNEL ROUTER WITH
HETEROGENEOUS ROUTER FOR ON CHIP NETWORK
6 CTJV106 ANALYSIS AND DESIGN OF A LOW-VOLTAGE LOW-POWER DOUBLE-TAIL COMPARATOR
7 CTJV107 EFFICENT RELIZATION OF DA BASED FIR FILTER USING VERILOG
8 CTJV108 A LOW-COST, SYSTEMATIC METHODOLOGY FOR SOFT ERROR ROBUSTNESS OF LOGIC CIRCUITS
9 CTJV109 ON-CHIP CODE WORD GENERATION TO COPE WITH CROSSTALK
10 CTJV110 LOW COMPLEXITY-HIGH THROUGHPUT QC-LDPC ENCODER
11 CTJV111 A NOVEL VLSI DHT ALGORITHAM FOR HIGHLY AND ACITECTURE MODELAR PARALEL
12 CTJV112 EXPLOITING SAME TAG BITS TO IMPROVE THE RELIABILITY OF THE CACHE MEMORIES
13 CTJV113 EFFICENT HARD WARE ARCHITUCTURE OF NT PAIRING ACELERATOR OVER CHARASTRICTIC TREE
14 CTJV114 CONSTRUCTIONS OF MEMORYLESS CROSSTALK AVOIDANCE CODES VIA C-TRANSFORM
15 CTJV115 AREA–DELAY–POWER EFFICIENT CARRY-SELECT ADDER
16 CTJV116 LOW-POWER PULSE-TRIGGERED FLIP-FLOP DESIGN BASED ON A SIGNAL FEED-THROUGH SCHEME
17 CTJV117 VLSI DESIGN OF LARGE NUMBER MULTIPLIER FOR FULLY HOMOMORPHIC ENCRYPTION
18 CTJV118 TEST PATTERNS OF MULTIPLE SIC VECTORS: THEORY AND APPLICATION IN BIST SCHEMES
19 CTJV119 ENERGY EFFICIENCY OPTIMIZATION THROUGH CODESIGN OF THE TRANSMITTER AND
RECEIVER IN HIGH-SPEEDON-CHIP INTERCONNECTS
20 CTJV120 A REAL-TIME MOTION-FEATURE-EXTRACTION VLSI EMPLOYING
DIGITAL-PIXEL-SENSOR-BASEDPARALLEL ARCHITECTURE
21 CTJV121 SELF-TIMED LOGIC AND THE DESIGN OF SELF-TIMED ADDERS
22 CTJV122 DESIGN AND DEVELOPMENT OF AUTOMATIC VISUAL INSPECTION SYSTEM
FOR PCB MANUFACTURING
23 CTJV123 AREA-DELAY-POWER EFFICIENT FIXED-POINT LMS ADAPTIVE FILTER
WITH LOW ADAPTATION-DELAY
24 CTJV124 FULLY REUSED VLSI ARCHITECTURE OF FM0/MANCHESTER ENCODING
USING SOLS TECHNIQUE FOR DSRC APPLICATIONS
25 CTJV125 FPGA DESING OF RECONFIGURABLE PROCESOR USING VLSI
26 CTJV126 AREA–DELAY–POWER EFFICIENT CARRY-SELECT ADDER
27 CTJV127 FAULT TOLERANT PARALLEL FILTERS BASED ON ERROR CORRECTION CODES
28 CTJV128 A HIGH PERFORMANCE DDR3 SDRAM CONTROLLER
29 CTJV129 VLSI IMPLEMENTATION OF IMAGE SCALING PROCESSOR
30 CTJV130 PORTABLE CAMERA BASED ASSISTINCE LABLE READING FOR BLIND PERSON
31 CTJV131 SOFTWARE/HARDWARE PARALLEL LONG-PERIOD RANDOM NUMBER
GENERATION FRAMEWORK BASED ON THE WELL METHOD
32 CTJV132 LOW-COMPLEXITY MULTIPLIER LESS CONSTANT ROTATORS BASED ON COMBINED
COEFFICIENT SELECTION AND SHIFT-AND-ADD IMPLEMENTATION (CCSSI)
33 CTJV133 A NOVEL APPROACH TO REALIZE BUILT-IN-SELF-TEST(BIST) ENABLED UART USING VHDL
34 CTJV134 AN OPTIMIZED MODIFIED BOOTH RECORDER FOR EFFICIENT DESIGN OF THE ADD-MULTIPLY OPERATOR
35 CTJV135 LOW-POWER PULSE-TRIGGERED FLIP-FLOP DESIGN BASED ON A SIGNAL FEED-THROUGH SCHEME
36 CTJV136 LOW-COMPLEXITY LOW-LATENCY ARCHITECTURE FOR MATCHING OF DATA ENCODED WITH
HARD SYSTEMATIC ERROR-CORRECTING CODES
37 CTJV137 DESIGN OF EFFICIENT BINARY COMPARATOR IN QUANTUM DOT CELLAR AUTOMATA
38 CTJV138 DATA ENCODING TECHNIQUES FOR REDUCING ENERGY CONSUMPTION IN NETWORK ON CHIP
39 CTJV139 SCALABLE DIGITAL COMOS COMPARATOR USING A PARALLEL PREFIX TREE


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