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B.TECH VLSI MINI PROJECTS LIST 2018 - 19

S.No Code PROJECT TITLE Download Titles Action
1 CT VL 101 Design of High Performance multiplier (8*8) using Vedic Multiplication Technique
2 CT VL 102 Design of FIR filter for Signal Processing Applications
3 CT VL 103 Design of Subtractor using Reversible gates
4 CT VL 104 Design a VLSI Architecture for Hamming decoder and encoder
5 CT VL 105 Design of Test Pattern Generator using LFSR
6 CT VL 106 Design a Baugh-Wooley Architecture for Signed and Unsigned Multiplication
7 CT VL 107 Design of Different Line Coding Techniques using Verilog
8 CT VL 108 Design of Asynchronous Counter using Verilog
9 CT VL 109 Design of Data Encryption Standard
10 CT VL 110 Design of Cyclic Redundancy Checker (CRC)
11 CT VL 111 Digital clock design using Verilog
12 CT VL 12 Digital Design of SIPO and PISO using Verilog
13 CT VL 13 Design of Fault Secure Encoder
14 CT VL 114 Design of Convolution using Verilog
15 CT VL 115 Design of Priority encoder using HDL
16 CT VL 116 Design of code converters using Verilog Programming
17 CT VL 117 Adiabatic Logic Based Low Power Multiplexer and De-multiplexer
18 CT VL 118 Clock gated 4-bit Johnson counter using low power JK flip flop
19 CT VL 119 Design of Parity Checker using Verilog
20 CT VL 120 Design of 16 bit Kogge Stone Adder and Spanning Tree Adder
21 CT VL 121 Double Fault tolerant Full adder design using Fault Localization
22 CT VL 122 Design and Simulation FFT (Fast Fourier Transform) using Radix 4
23 CT VL 123 Design of Carry Tree Adder using Verilog
24 CT VL 124 Design of High Speed Multiplier with Barrel Shifter
25 CT VL 125 Realization of Gates using MUX using CMOS Technology
26 CT VL 126 Design of Dual Port SRAM
27 CT VL 127 Design of Matrix Multiplication using Verilog
28 CT VL 128 Design of SHA using Verilog
29 CT VL 129 Design of Shift Register using Pulsed Latches
30 CT VL 130 Design of 8 bit ALU using Reversible Gates
31 CT VL 131 Design And Synthesis of Programmable Logic Block
32 CT VL 132 Design Traffic Light Controller using FSM with Verilog
33 CT VL 133 Design of Parallel self-timed adder
34 CT VL 134 Design of Vending Machine using FSM
35 CT VL 135 Design of Mealy and Moore type Serial Adders
36 CT VL 136 Design of 8 bit QPSK Modulation Technique
37 CT VL 137 Design and synthesis of combinational circuits using reversible decoder in Xilinx
38 CT VL 138 Optimal Design of Reversible Parity Preserving New Full adder / full subtractor
39 CT VL 139 A Rule based approach for minimizing power dissipation of Digital circuits
40 CT VL 140 Design and analysis of multiplier using approximate 15-4 compressor
41 CT VL 141 Comparison and analysis of combinational circuits using different logic styles
42 CT VL 142 Design of Multiplexer using Reversible Gates
43 CT VL 143 Design of 8 bit LFSR for Arithmetic Operations
44 CT VL 144 Design of Sequence Detector using FSM
45 CT VL 145 Design of Clock Divider using Verilog Programming
46 CT VL 146 Verilog code for Parking system using FSM
47 CT VL 147 Design of comparator using Verilog
48 CT VL 148 Design of carry select adder
49 CT VL 149 Design of Binary to Gray Counter using Verilog
50 CT VL 150 Design of FIFO using HDL

B.TECH VLSI MINI PROJECTS LIST 2017 - 18

S.No Code PROJECT TITLE Download Titles Action
1 CT VL 101 Design the High Speed Kogge-Stone Adder by Using Multiplexer
2 CT VL 102 Design of 16 bit spanning tree carry look ahead adder
3 CT VL 103 Design of 16 point Radix-4 FFT Algorithm
4 CT VL 104 Design of ATM(Automated Teller Machine)
5 CT VL 105 A spurious power suppression technique for multimedia DSP applications
6 CT VL 106 Design of carry select adder
7 CT VL 107 Design of dual elevator controller
8 CT VL 108 Design of RCEAT for RFID Tag
9 CT VL 109 Design of 16 bit Ripple Carry Adder
10 CT VL 110 Design of dual port SRAM
11 CT VL 1 Multiplication Acceleration through Twin Precision
12 CT VL 112 Design of vending machine
13 CT VL 113 Design of complex number multiplier using Booth Algorithm
14 CT VL 14 Design and implementation of 8 point FFT
15 CT VL 115 Design of digital clock
16 CT VL 116 Design of AMBA-AHB protocol
17 CT VL 117 Design of DDRSD RAM controller
18 CT VL 118 Implementation of Traffic Light controller
19 CT VL 119 Implementation of dual port RAM
20 CT VL 120 Implementation of Universal Asynchronous Receiver/Transmitter(UART)
21 CT VL 121 Implementation of 16 bit Carry Look Ahead Adder for Fast addition
22 CT VL 122 Implementation of 16 bit Carry Save Adder for Fast addition
23 CT VL 123 Implementation of 16 bit Pseudo Random Test Pattern Generator
24 CT VL 124 Implementation of Melay type and Moore type serial adders
25 CT VL 125 Implementation of 16 Bit Braun Multipliers
26 CT VL 126 Implementation of Matrix Multiplication
27 CT VL 127 Implementation of Cyclic Redundancy Check
28 CT VL 128 Implementation of 16 bit Wallace tree multiplier
29 CT VL 129 Implementation of 4 bit ALU
30 CT VL 130 An interface between on chip and off chip
31 CT VL 131 Low power Multiplier using Ancient Mathematics
32 CT VL 132 Implementation of Hamming code using Verilog
33 CT VL 133 Design and Implementation of convolution
34 CT VL 134 Design of 16-bit QPSK (Quadrature Phase Shift Keying)
35 CT VL 135 Design of Data Encryption Standard (DES)
36 CT VL 136 Design of JPEG Image compression standard
37 CT VL 137 Adiabatic Technique For Energy Efficient Logic Circuits Design
38 CT VL 138 Implementation of discrete wavelet transform
39 CT VL 139 ASIC Design of Complex multiplier
40 CT VL 140 Design of Finite Impulse Response Filter
41 CT VL 141 4 BIT SFQ Multiplier
42 CT VL 142 LFSR based test Generator synthesis
43 CT VL 143 Asynchronous Transfer mode Knockout Switch
44 CT VL 144 Rotation based BIST with self feedback
45 CT VL 145 Soft Error Tolerance and Mitigation
46 CT VL 146 Design and synthesis of programmable logic block
47 CT VL 147 Fault Secure Encoder
48 CT VL 148 Shift Register Based Data Transposition
49 CT VL 149 Short range MIMO communications
50 CT VL 150 Low power ALU design by using Ancient Mathematics
51 CT VL 151 Image compression standards for DSP applications
52 CT VL 152 Implementation of seven segment display and code converters

B.TECH VLSI MINI PROJECTS LIST 2016 - 17

S.No Code PROJECT TITLE Download Titles Action
1 CT VL101 SPEED OPTIMIZATION OF A FPGA BASED MODIFIED VITERBI DECODER
2 CT VL102 VLSI IMPLEMENTATION OF BOOTHS ALGORITHM USING FPGA WITH VERILOG
3 CT VL103 DESIGN AND IMPLEMENTATION OF ALU USING HDL
4 CT VL104 DESIGN AND IMPLEMENTATION OF ERROR DETECTOR AND CORRECTOR (EDAC) UNIT USING HDL
5 CT VL105 DESIGN AND MODELING OF I2C BUS CONTROLLER
6 CT VL106 AN EFFICIENT ARCHITECTURE FOR 2-D LIFTING-BASED DISCRETE WAVELET TRANSFORM
7 CT VL107 EFFICIENT FPGA IMPLEMENTATION OF CONVOLUTION
8 CT VL108 A MEMORY-EFFICIENT HUFFMAN DECODING ALGORITHM
9 CT VL109 DESIGN OF AN ATM (AUTOMATED TELLER MACHINE) CONTROLLER
10 CT VL110 DESIGN AND VERIFICATION OF 8 BIT HAMMING ENCODER AND DECODER
11 CT VL111 DESIGN OF LOW POWER HIGH SPEED VLSI ADDER SUBSYSTEM
12 CT VL112 MODIFIED WALLACE TREE MULTIPLIER USING EFFICIENT SQUARE ROOT CARRY SELECT ADDER
13 CT VL113 SHIFT REGISTER DESIGN USING TWO BIT FLIP-FLOP
14 CT VL114 DESIGN OF DUAL ELEVATOR CONTROLLER
15 CT VL115 DESIGN OF 8-BIT QPSK (QUADRATURE PHASE SHIFT KEYING)
16 CT VL116 DESIGN OF DIGITAL FM RECEIVER USING PLL (PHASE LOCKED LOOP)
17 CT VL117 HIGH-PERFORMANCE 16-BIT BINARY COMPARATOR
18 CT VL118 A GENERALIZATION OF ADDITION CHAINS AND FAST INVERSIONS IN BINARY FIELDS
19 CT VL119 LOW-POWER AND AREA-EFFICIENT SHIFT REGISTER USING PULSED LATCHES
20 CT VL120 AN OPTIMIZED MODIFIED BOOTH RECODER FOR EFFICIENT DESIGN OF THE ADD-MULTIPLY
OPERATOR
21 CT VL121 AREA-DELAY EFFICIENT BINARY ADDER IN QCA
22 CT VL122 NOVEL HIGH SPEED VEDIC MATHEMATICS MULTIPLIER USING COMPRESSORS
23 CT VL123 IMPLEMENTATION OF TRAFFIC LIGHT CONTROLLER
24 CT VL124 IMPLEMENTATION OF MEALY TYPE MOORE TYPE SERIAL ADDERS
25 CT VL125 DESIGN AND IMPLEMENTATION OF DIGITAL CODE LOCK USING VERILOG
26 CT VL126 VLSI COMPUTATIONAL ARCHITECTURES FOR THE ARITHMETIC COSINE TRANSFORM
27 CT VL127 EFFICIENT CODING SCHEMES FOR FAULT-TOLERANT PARALLEL FILTERS
28 CT VL128 RAIL-PASSENGER INFORMATION SYSTEM
29 CT VL129 DESIGN OF KOGGE-STONE ADDER
30 CT VL130 DESIGN OF VENDING MACHINE
31 CT VL131 IMPLEMENTATION OF MATRIX MULTIPLICATION
32 CT VL132 IMPLEMENTATION OF SEVEN SEGMENT DISPLAY AND CODE CONVERTORS
33 CT VL133 DESIGN AND IMPLEMENTATION OF LFSR FOR LOW POWER APPLICATIONS USING VERILOG
34 CT VL134 DESIGN OF RECONFIGURABLE COPROCESSOR FOR COMMUNICATION SYSTEMS
35 CT VL135 DESIGN OF KEYBOARD CONTROLLER
36 CT VL136 DESIGN OF AN ATP (ANY TIME PAYMENT) MACHINE FOR ELECTRICITY BILL PAYMENT APPLICATION
37 CT VL137 DESIGN AND IMPLEMENTATION OF ELECTRONIC VOTING MACHINE DESIGN USING HDL
38 CT VL138 DESIGN AND IMPLEMENTATION OF SIGNED ADDER, SUBTRACTOR USING HDL
39 CT VL139 NOVEL SQUARE ROOT ALGORITHM AND ITS IMPLEMENTATION USING VERILOG
40 CT VL140 DESIGN AND IMPLEMENTATION OF UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
41 CT VL141 FAULT SECURE ENCODER AND DECODER FOR NANO-MEMORY APPLICATIONS
42 CT VL142 IMPLEMENTATION OF CARRY TREE ADDER
43 CT VL143 A LOW COMPLEXITY TURBO DECODER ARCHITECTURE FOR ENERGY-EFFICIENT WIRELESS SENSOR NETWORKS
44 CT VL144 FPGA IMPLEMENTATION OF MULTI OPERAND REDUNDANT ADDERS
45 CT VL145 MULTI BIT FLIP-FLOP DESIGN FOR AREA EFFICIENCY
46 CT VL146 CONSTANT AND HIGH SPEED ADDER DESIGN USING QSD NUMBER SYSTEM
47 CT VL147 A COMMON BOOLEAN LOGIC(CBL) IMPLEMENTATION FOR MODIFIED CSLA
48 CT VL148 HIGH SPEED VEDIC MULTIPLIER USING BARREL SHIFTER
49 CT VL149 A FLOATING POINT FUSED DOT PRODUCT UNIT
50 CT VL150 LUT OPTIMIZATION FOR MEMORY-BASED COMPUTATION
51 CT VL151 A NOVEL NANO-METRIC PARITY PRESERVING REVERSIBLE VEDIC MULTIPLIER
52 CT VL152 PULSE TRIGGERED FLIP-FLOP DESIGN FOR LOW POWER
53 CT VL153 BEHAVIORAL SYNTHESIS OF ASYNCHRONOUS CIRCUITS
54 CT VL154 DUAL DATA RATE SD RAM 3 CONTROLLER
55 CT VL155 A FRAMEWORK FOR CORRECTION OF MULTI-BIT SOFT ERRORS
56 CT VL156 MINIMIZATION OF SWITCHING ACTIVITIES OF PARTIAL PRODUCTS FOR
DESIGNING LOW-POWER MULTIPLIERS
57 CT VL157 DESIGN AND VERIFICATION OF BLUETOOTH BASE BAND CONTROLLER
58 CT VL158 ADVANCED ENCRYPTION SYSTEM TO IMPROVISE THE SYSTEM COMPUTING SPEED
59 CT VL159 DESIGN OF CACHE MEMORY WITH CACHE CONTROLLER USING VHDL
60 CT VL160 FPGA IMPLEMENTATION OF MUTUAL AUTHENTICATION PROTOCOL USING MODULAR ARITHMETIC
61 CT VL161 IMPLEMENTATION OF OVERLAP BASED LOGIC CELL AND ITS POWE ANALYSIS
62 CT VL162 LOW POWER AND HIGH SPEED CONDITIONAL PUSH-PULL PULSED LATCHES
63 CT VL163 AN ENHANCED LOW COST HIGH PERFORMANCE IMAGE SCALING PROCESSOR USING VLSI
64 CT VL164 PERFORMANCE ANALYSIS OF HIGH EFFICIENCY LOW DENSITY PARITY-CHECK CODE DECODER FOR
LOW POWER APPLICATIONS
65 CT VL165 A NOVEL APPROACH TO REALIZE BUILT-IN-SELF-TEST(BIST) ENABLED UART USING VERILOG
66 CT VL166 LOW COMPLEXITY LOW LATENCY ARCHITECTURE FOR MATCHING OF DATA ENCODED WITH
HARD SYSTEMATIC ERROR CORRECTING CODES
67 CT VL167 IMPLEMENTATION OF HIGH-SPEED PIPELINE VLSI ARCHITECTURES
68 CT VL168 VLSI IMPLEMENTATION OF ADDRESS GENERATION COPROCESSOR
69 CT VL169 VLSI DESIGN & IMPLEMENTATION OF SECURE TRANSMITTING AND RECEIVING
TEXT DATA IN COMMUNICATION SYSTEMS USING VERILOG/VHDL CODE
70 CT VL170 ASIC DESIGN OF COMPLEX MULTIPLIER
71 CT VL171 LOW-POWER AND AREA-EFFICIENT CARRY SELECT ADDER
72 CT VL172 DESIGN AND SYNTHESIS OF PROGRAMMABLE LOGIC BLOCK
73 CT VL173 DESIGNING EFFICIENT ONLINE TESTABLE REVERSIBLE ADDERS
74 CT VL174 DESIGN AND IMPLEMENTATION OF SEQUENCE DETECTOR USING HDL
75 CT VL 175 DESIGN AND IMPLEMENTATION OF LOOK AHEAD CARRY GENERATOR USING HDL

B.TECH VLSI MINI PROJECTS LIST 2015 - 16

S.No Code PROJECT TITLE Download Titles Action
1 CT VL 101 SPEED OPTIMIZATION OF A FPGA BASED MODIFIED VITERBI DECODER
2 CT VL 102 VLSI IMPLEMENTATION OF BOOTHS ALGORITHM USING FPGA WITH VERILOG
3 CT VL 103 DESIGN AND IMPLEMENTATION OF ALU USING HDL
4 CT VL 104 DESIGN AND IMPLEMENTATION OF ERROR DETECTOR AND CORRECTOR (EDAC) UNIT USING HDL
5 CT VL 105 DESIGN AND MODELING OF I2C BUS CONTROLLER
6 CT VL 106 AN EFFICIENT ARCHITECTURE FOR 2-D LIFTING-BASED DISCRETE WAVELET TRANSFORM
7 CT VL 107 EFFICIENT FPGA IMPLEMENTATION OF CONVOLUTION
8 CT VL 108 A MEMORY-EFFICIENT HUFFMAN DECODING ALGORITHM
9 CT VL 109 DESIGN OF AN ATM (AUTOMATED TELLER MACHINE) CONTROLLER
10 CT VL 110 DESIGN AND VERIFICATION OF 8 BIT HAMMING ENCODER AND DECODER
11 CT VL 111 DESIGN OF LOW POWER HIGH SPEED VLSI ADDER SUBSYSTEM
12 CT VL 112 MODIFIED WALLACE TREE MULTIPLIER USING EFFICIENT SQUARE ROOT CARRY SELECT ADDER
13 CT VL 113 SHIFT REGISTER DESIGN USING TWO BIT FLIP-FLOP
14 CT VL 114 DESIGN OF DUAL ELEVATOR CONTROLLER
15 CT VL 115 DESIGN OF 8-BIT QPSK (QUADRATURE PHASE SHIFT KEYING)
16 CT VL 116 DESIGN OF DIGITAL FM RECEIVER USING PLL (PHASE LOCKED LOOP)
17 CT VL 117 HIGH-PERFORMANCE 16-BIT BINARY COMPARATOR
18 CT VL 118 A GENERALIZATION OF ADDITION CHAINS AND FAST INVERSIONS IN BINARY FIELDS
19 CT VL 119 LOW-POWER AND AREA-EFFICIENT SHIFT REGISTER USING PULSED LATCHES
20 CT VL 120 AN OPTIMIZED MODIFIED BOOTH RECODER FOR EFFICIENT DESIGN OF THE ADD-MULTIPLY
OPERATOR
21 CT VL 121 AREA-DELAY EFFICIENT BINARY ADDER IN QCA
22 CT VL 122 NOVEL HIGH SPEED VEDIC MATHEMATICS MULTIPLIER USING COMPRESSORS
23 CT VL 123 IMPLEMENTATION OF TRAFFIC LIGHT CONTROLLER
24 CT VL 124 IMPLEMENTATION OF MEALY TYPE MOORE TYPE SERIAL ADDERS
25 CT VL 125 DESIGN AND IMPLEMENTATION OF DIGITAL CODE LOCK USING VERILOG
26 CT VL 126 VLSI COMPUTATIONAL ARCHITECTURES FOR THE ARITHMETIC COSINE TRANSFORM
27 CT VL 127 EFFICIENT CODING SCHEMES FOR FAULT-TOLERANT PARALLEL FILTERS
28 CT VL 128 RAIL-PASSENGER INFORMATION SYSTEM
29 CT VL 129 DESIGN OF KOGGE-STONE ADDER
30 CT VL 130 DESIGN OF VENDING MACHINE
31 CT VL 131 IMPLEMENTATION OF MATRIX MULTIPLICATION
32 CT VL 132 IMPLEMENTATION OF SEVEN SEGMENT DISPLAY AND CODE CONVERTORS
33 CT VL 133 DESIGN AND IMPLEMENTATION OF LFSR FOR LOW POWER APPLICATIONS USING VERILOG
34 CT VL 134 DESIGN OF RECONFIGURABLE COPROCESSOR FOR COMMUNICATION SYSTEMS
35 CT VL 135 DESIGN OF KEYBOARD CONTROLLER
36 CT VL 136 DESIGN OF AN ATP (ANY TIME PAYMENT) MACHINE FOR ELECTRICITY BILL PAYMENT APPLICATION
37 CT VL 137 DESIGN AND IMPLEMENTATION OF ELECTRONIC VOTING MACHINE DESIGN USING HDL
38 CT VL 138 DESIGN AND IMPLEMENTATION OF SIGNED ADDER, SUBTRACTOR USING HDL
39 CT VL 139 NOVEL SQUARE ROOT ALGORITHM AND ITS IMPLEMENTATION USING VERILOG
40 CT VL 140 DESIGN AND IMPLEMENTATION OF UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
41 CT VL 141 FAULT SECURE ENCODER AND DECODER FOR NANO-MEMORY APPLICATIONS
42 CT VL 142 IMPLEMENTATION OF CARRY TREE ADDER
43 CT VL 143 A LOW COMPLEXITY TURBO DECODER ARCHITECTURE FOR ENERGY-EFFICIENT WIRELESS
SENSOR NETWORKS
44 CT VL 144 FPGA IMPLEMENTATION OF MULTI OPERAND REDUNDANT ADDERS
45 CT VL 145 MULTI BIT FLIP-FLOP DESIGN FOR AREA EFFICIENCY
46 CT VL 146 CONSTANT AND HIGH SPEED ADDER DESIGN USING QSD NUMBER SYSTEM
47 CT VL 147 A COMMON BOOLEAN LOGIC(CBL) IMPLEMENTATION FOR MODIFIED CSLA
48 CT VL 148 HIGH SPEED VEDIC MULTIPLIER USING BARREL SHIFTER
49 CT VL 149 A FLOATING POINT FUSED DOT PRODUCT UNIT
50 CT VL 150 LUT OPTIMIZATION FOR MEMORY-BASED COMPUTATION
51 CT VL 151 A NOVEL NANO-METRIC PARITY PRESERVING REVERSIBLE VEDIC MULTIPLIER
52 CT VL 152 PULSE TRIGGERED FLIP-FLOP DESIGN FOR LOW POWER
53 CT VL 153 BEHAVIORAL SYNTHESIS OF ASYNCHRONOUS CIRCUITS
54 CT VL 154 DUAL DATA RATE SD RAM 3 CONTROLLER
55 CT VL 155 A FRAMEWORK FOR CORRECTION OF MULTI-BIT SOFT ERRORS
56 CT VL 156 MINIMIZATION OF SWITCHING ACTIVITIES OF PARTIAL PRODUCTS FOR
DESIGNING LOW-POWER MULTIPLIERS
57 CT VL 157 DESIGN AND VERIFICATION OF BLUETOOTH BASE BAND CONTROLLER
58 CT VL 158 ADVANCED ENCRYPTION SYSTEM TO IMPROVISE THE SYSTEM COMPUTING SPEED
59 CT VL 159 DESIGN OF CACHE MEMORY WITH CACHE CONTROLLER USING VHDL
60 CT VL 160 FPGA IMPLEMENTATION OF MUTUAL AUTHENTICATION PROTOCOL USING MODULAR ARITHMETIC
61 CT VL 161 IMPLEMENTATION OF OVERLAP BASED LOGIC CELL AND ITS POWE ANALYSIS
62 CT VL 162 LOW POWER AND HIGH SPEED CONDITIONAL PUSH-PULL PULSED LATCHES
63 CT VL 163 AN ENHANCED LOW COST HIGH PERFORMANCE IMAGE SCALING PROCESSOR USING VLSI
64 CT VL 164 PERFORMANCE ANALYSIS OF HIGH EFFICIENCY LOW DENSITY PARITY-CHECK
CODE DECODER FOR LOW POWER APPLICATIONS
65 CT VL 165 A NOVEL APPROACH TO REALIZE BUILT-IN-SELF-TEST(BIST) ENABLED UART USING VERILOG
66 CT VL 166 LOW COMPLEXITY LOW LATENCY ARCHITECTURE FOR MATCHING OF DATA ENCODED
WITH HARD SYSTEMATIC ERROR CORRECTING CODES
67 CT VL 167 IMPLEMENTATION OF HIGH-SPEED PIPELINE VLSI ARCHITECTURES
68 CT VL 168 VLSI IMPLEMENTATION OF ADDRESS GENERATION COPROCESSOR
69 CT VL 169 VLSI DESIGN & IMPLEMENTATION OF SECURE TRANSMITTING AND RECEIVING TEXT DATA
IN COMMUNICATION SYSTEMS USING VERILOG/VHDL CODE
70 CT VL 170 ASIC DESIGN OF COMPLEX MULTIPLIER
71 CT VL 171 LOW-POWER AND AREA-EFFICIENT CARRY SELECT ADDER
72 CT VL 172 DESIGN AND SYNTHESIS OF PROGRAMMABLE LOGIC BLOCK
73 CT VL 173 DESIGNING EFFICIENT ONLINE TESTABLE REVERSIBLE ADDERS
74 CT VL 174 DESIGN AND IMPLEMENTATION OF SEQUENCE DETECTOR USING HDL
75 CT VL 175 DESIGN AND IMPLEMENTATION OF LOOK AHEAD CARRY GENERATOR USING HDL
76 CT VL 176 DESIGN AND IMPLEMENTATION OF CARRY SAVE ARRAY ARITHMETIC MULTIPLIER
77 CT VL 177 DESIGN OF REVERSIBLE LOGIC GATES AND THEIR IMPLEMENTATION
78 CT VL 178 RS 232 LOGIC DESIGN ON VLSI PLATFORM
79 CT VL 179 AGING-AWARE RELIABLE MULTIPLIER DESIGN WITH ADAPTIVE HOLD LOGIC
80 CT VL 180 VERILOG IMPLEMENTATION OF RECONFIGURABLE ROUTER (NOC)
81 CT VL 181 DEVELOPMENT AND VERIFICATION OF SPI PROTOCOL
82 CT VL 182 DESIGN OF CONTROL AREA NETWORK PROTOCOL

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